|
Hardware Support for Efficient Packet Processing
Geib, Benjamin Ulrich
![[img]](https://madoc.bib.uni-mannheim.de/style/images/fileicons/application_pdf.png)  Vorschau |
|
PDF
dissertation_benjamin_geib.pdf
- Veröffentlichte Version
Download (10MB)
|
|
URL:
|
https://ub-madoc.bib.uni-mannheim.de/30849
|
|
URN:
|
urn:nbn:de:bsz:180-madoc-308492
|
|
Dokumenttyp:
|
Dissertation
|
|
Erscheinungsjahr:
|
2012
|
|
Ort der Veröffentlichung:
|
Mannheim
|
|
Verlag:
|
Universität Mannheim
|
|
Hochschule:
|
Universität Mannheim
|
|
Gutachter:
|
Brüning, Ulrich
|
|
Datum der mündl. Prüfung:
|
21 März 2012
|
|
Sprache der Veröffentlichung:
|
Englisch
|
|
Einrichtung:
|
Fakultät für Wirtschaftsinformatik und Wirtschaftsmathematik > Rechnerarchitektur (Brüning 1996-2008)
|
|
Fachgebiet:
|
004 Informatik
|
|
Normierte Schlagwörter (SWD):
|
Hardwareentwurf , Verbindungsstruktur , Hochleistungsrechnen
|
|
Freie Schlagwörter (Englisch):
|
Packet Processing , Low Latency , Tag Matching , Crossbar , Hardware Design , Interconnection Network , Computer Architecture , High Performance Computing
|
|
Abstract:
|
Scalability is the key ingredient to further increase the performance of today’s supercomputers.
As other approaches like frequency scaling reach their limits, parallelization is the
only feasible way to further improve the performance. The time required for communication
needs to be kept as small as possible to increase the scalability, in order to be able to
further parallelize such systems.
In the first part of this thesis ways to reduce the inflicted latency in packet based interconnection
networks are analyzed and several new architectural solutions are proposed to
solve these issues. These solutions have been tested and proven in a field programmable
gate array (FPGA) environment. In addition, a hardware (HW) structure is presented that
enables low latency packet processing for financial markets.
The second part and the main contribution of this thesis is the newly designed crossbar
architecture. It introduces a novel way to integrate the ability to multicast in a crossbar
design. Furthermore, an efficient implementation of adaptive routing to reduce the
congestion vulnerability in packet based interconnection networks is shown. The low
latency of the design is demonstrated through simulation and its scalability is proven with
synthesis results.
The third part concentrates on the improvements and modifications made to EXTOLL, a
high performance interconnection network specifically designed for low latency and high
throughput applications. Contributions are modules enabling an efficient integration of
multiple host interfaces as well as the integration of the on-chip interconnect. Additionally,
some of the already existing functionality has been revised and improved to reach better
performance and a lower latency. Micro-benchmark results are presented to underline the
contribution of the made modifications.
|
 | Das Dokument wird vom Publikationsserver der Universitätsbibliothek Mannheim bereitgestellt. |
 Suche Autoren in
Sie haben einen Fehler gefunden? Teilen Sie uns Ihren Korrekturwunsch bitte hier mit: E-Mail
Actions (login required)
 |
Eintrag anzeigen |
|
|
