Cycle time optimization by timing driven placement with simultaneous netlist transformations

  • We present new concepts to integrate logic synthesis and physical design. Our methodology uses general Boolean transformations as known from technology-independent synthesis, and a recursive bi-partitioning placement algorithm. In each partitioning step, the precision of the layout data increases. This allows effective guidance of the logic synthesis operations for cycle time optimization. An additional advantage of our approach is that no complicated layout corrections are needed when the netlist is changed.

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Metadaten
Author:Hendrik Hartje, Ingmar Neumann, Dominik Stoffel, Wolfgang Kunz
URN:urn:nbn:de:hebis:30-25185
ISBN:0-7803-6685-9
Parent Title (German):Proc. of the IEEE International Symposium on Circuits and Systems, (ISCAS) Feb. 5-9 2001, Sydney, Australia
Document Type:Conference Proceeding
Language:English
Date of Publication (online):2006/03/21
Year of first Publication:2001
Publishing Institution:Universitätsbibliothek Johann Christian Senckenberg
Release Date:2006/03/21
First Page:V-359
Last Page:V-362
Source:Proc. of the IEEE International Symposium on Circuits and Systems, (ISCAS) Feb. 5-9 2001, Sydney, Australia, ©2001 IEEE
HeBIS-PPN:226454509
Institutes:Informatik und Mathematik / Informatik
Dewey Decimal Classification:0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 004 Datenverarbeitung; Informatik
Licence (German):License LogoDeutsches Urheberrecht