- AutorIn
- Bhaveen Lodaya
- Titel
- On-Board Memory Extension on Reconfigurable Integrated Circuits using External DDR3 Memory
- Untertitel
- On-Board Memory Extension on Reconfigurable Integrated Circuits usingExternal DDR3 Memory
- Zitierfähige Url:
- https://nbn-resolving.org/urn:nbn:de:bsz:ch1-qucosa-233196
- Abstract (EN)
- User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization. One drawback of FPGA-based data exploitation is the limited memory capacity of reconfigurable integrated circuits. Large-scale Digital Signal Processor (DSP) FPGAs provide approximately 4MB on-board random access memory (RAM) which is not sufficient to buffer the broadband sensor and result data. Hence, additional external memory is connected to the FPGA to increase on-board storage capacities. External memory devices like double data rate three synchronous dynamic random access memories (DDR3-SDRAM) provide very fast and wide bandwidth interfaces that represent a bottleneck when used in highly parallelized processing architectures. Independent processing modules are demanding concurrent read and write access. Within the master thesis, a concept for the integration of an external DDR3- SDRAM into an FPGA-based parallelized processing architecture is developed and implemented. The solution realizes time division multiple access (TDMA) to the external memory and virtual, low-latency memory extension to the on-board buffer capabilities. The integration of the external RAM does not change the way how on-board buffers are used (control, data-fow).
- Freie Schlagwörter (DE)
- FPGA, DDR3-SRAM, parallele Verarbeitung
- Freie Schlagwörter (EN)
- DDR3- SDRAM, FPGA, parallelized processing architecture
- Klassifikation (DDC)
- 004
- Normschlagwörter (GND)
- Informatik, Field programmable gate array, TDMA
- GutachterIn
- Dipl.-Ing. Stephan Blokzyl
- Prof. Dr. Wolfram Hardt
- BetreuerIn
- Dipl.-Ing. Stephan Blokzyl
- Prof. Dr. Wolfram Hardt
- Den akademischen Grad verleihende / prüfende Institution
- Technische Universität Chemnitz, Chemnitz
- URN Qucosa
- urn:nbn:de:bsz:ch1-qucosa-233196
- Veröffentlichungsdatum Qucosa
- 08.02.2018
- Dokumenttyp
- Masterarbeit / Staatsexamensarbeit
- Sprache des Dokumentes
- Englisch