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The shift from processor power consumption to performance variations: fundamental implications at scale

  • Special Issue Paper
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Computer Science - Research and Development

Abstract

The Intel Haswell-EP processor generation introduces several major advancements of power control and energy-efficiency features. For computationally intense applications using advanced vector extension instructions, the processor cannot continuously operate at full speed but instead reduces its frequency below the nominal frequency to maintain operations within thermal design power (TDP) limitations. Moreover, the running average power limitation (RAPL) mechanism to enforce the TDP limitation has changed from a modeling to a measurement approach. The combination of these two novelties have significant implications. Through measurements on an Intel Sandy Bridge-EP cluster, we show that previous generations have sustained homogeneous performance across multiple CPUs and compensated for hardware manufacturing variability through varying power consumption. In contrast, our measurements on a Petaflop Haswell system show that this generation exhibits rather homogeneous power consumption limited by the TDP and capped by the improved RAPL while providing inhomogeneous performance under full load. Since all of these controls are transparent to the user, this behavior is likely to complicate performance analysis tasks and impact tightly coupled parallel applications.

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References

  1. Borkar, S.: Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro (2005). doi:10.1109/MM.2005.110

  2. Borkar S, Karnik T, Narendra S, Tschanz J, Keshavarzi A, De V (2003) Parameter variations and impact on circuits and microarchitecture. In: Proceedings of the 40th annual design automation conference. doi:10.1145/775832.775920

  3. Cooled with warm water—Bullx DLC B700 series (factsheet). http://www.bull.com/sites/default/files/docs-dl/f-bullxb700-en7.pdf. Accessed Dec 2015

  4. Hackenberg D, Ilsche T, Schöne R, Molka D, Schmidt M, Nagel W (2013) Power measurement techniques on standard compute nodes: a quantitative comparison. In: International symposium on performance analysis of systems and software (ISPASS). doi:10.1109/ISPASS.2013.6557170

  5. Hackenberg D, Ilsche T, Schuchart J, Schöne R, Nagel W, Simon M, Georgiou Y (2014) HDEEM: high definition energy efficiency monitoring. In: Energy efficient supercomputing workshop (E2SC). doi:10.1109/E2SC.2014.13

  6. Hackenberg D, Oldenburg R, Molka D, Schöne R (2013) Introducing FIRESTARTER: a processor stress test utility. doi:10.1109/igcc.2013.6604507

  7. Hackenberg D, Schöne R, Ilsche T, Molka D, Schuchart J, Geyer R (2015) An energy efficiency feature survey of the intel Haswell processor. In: International parallel and distributed processing symposium workshop (IPDPSW). doi:10.1109/IPDPSW.2015.70

  8. Intel Corporation: Intel Xeon Processor E5 v3 Product Familiy. processor specification update (2015)

  9. Optimizing performance with intel advanced vector extensions: Intel Corporation (2014)

  10. Pedretti K, Olivier SL, Ferreira KB, Shipman G, Shu W (2015) Early experiences with node-level power capping on the Cray XC40 platform. In: Proceedings of the 3rd international workshop on energy efficient supercomputing. doi:10.1145/2834800.2834801

  11. Rotem E, Naveh A, Rajwan D, Ananthakrishnan A, Weissmann E (2012) Power-management architecture of the intel microarchitecture code-named sandy bridge. IEEE Micro. doi:10.1109/MM.2012.12

  12. Rountree B, Ahn DH, De Supinski BR, Lowenthal DK, Schulz M (2012) Beyond DVFS: a first look at performance under a hardware-enforced power bound. In: Parallel and distributed processing symposium workshops (IPDPSW). doi:10.1109/IPDPSW.2012.116

  13. Russell J, Cohn R (2012) Prime95. Book on demand. http://books.google.de/books?id=IsHUMgEACAAJ

  14. Scogland T, Azose J, Rohr D, Rivoire S, Bates N, Hackenberg D (2015) Node variability in large-scale power measurements: perspectives from the Green500, Top500 and EEHPCWG. In: International conference for high performance computing, networking, storage and analysis (supercomputing). doi:10.1145/2807591.2807653

  15. Wilde T, Auweter A, Shoukourian H, Bode A (2015) Taking advantage of node power variation in homogenous HPC systems to save energy. In: ISC high performance. doi:10.1007/978-3-319-20119-1_27

  16. Zhang H, Hoffmann H (2015) A quantitative evaluation of the RAPL power control. In: 10th international workshop on feedback computing. http://people.cs.uchicago.edu/~hankhoffmann/FC2015.pdf

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Acknowledgments

This work has been funded in a part by the German Research Foundation (DFG) in the Collaborative Research Center “Highly Adaptive Energy-Efficient Computing” (HAEC, SFB 912) and by the European Union’s Horizon 2020 Programme in the READEX project under Grant Agreement Number 671657.

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Correspondence to Joseph Schuchart.

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Schuchart, J., Hackenberg, D., Schöne, R. et al. The shift from processor power consumption to performance variations: fundamental implications at scale. Comput Sci Res Dev 31, 197–205 (2016). https://doi.org/10.1007/s00450-016-0327-2

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  • DOI: https://doi.org/10.1007/s00450-016-0327-2

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