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Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors

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Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

Upcoming multi-media compression applications will require high memory bandwidth. In this paper, we estimate that a software reference implementation of an MPEG-4 video decoder typically requires 200 Mtransfers/s to memory to decode 1 CIF (352×288) Video Object Plane (VOP) at 30 frames/s. This imposes a high penalty in terms of power but also performance.

However, we also show that we can heavily improve on the memory transfers, without sacrificing speed (even gaining about 10% on cache misses and cycles for a DEC Alpha), by aggressive code transformations. For this purpose, we have manually applied an extended version of our data transfer and storage exploration (DTSE) methodology, which was originally developed for custom hardware implementations.

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Authors and Affiliations

  1. Interuniversity Micro Electronics Centrum (IMEC), Leuven, Belgium

    Lode Nachtergaele, Toon Gijbels, Jan Bormans, Francky Catthoor & Ivo Bolsens

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  1. Lode Nachtergaele
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  2. Toon Gijbels
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  3. Jan Bormans
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  4. Francky Catthoor
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  5. Ivo Bolsens
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Nachtergaele, L., Gijbels, T., Bormans, J. et al. Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 27, 161–169 (2001). https://doi.org/10.1023/A:1008135917341

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