Abstract
Body-area sensor network or BAN-based health monitoring is increasingly becoming a popular alternative to traditional wired bio-monitoring techniques. However, most biomonitoring applications need continuous processing of large volumes of data, as a result of which both power consumption and computation bandwidth turn out to be serious constraints for sensor network platforms. This has resulted in a lot of recent interest in design methods, modeling and software analysis techniques specifically targeted towards BANs and applications running on them. In this paper we show that appropriate optimization of the application running on the communication gateway of a wireless BAN and accurate modeling of the microarchitectural details of the gateway processor can lead to significantly better resource usage and power savings. In particular, we propose a method for deriving the optimal order in which the different sensors feeding the gateway processor should be sampled, to maximize cache reuse. In addition, we also investigate the effects on cache reuse of different memory layouts of the code processing the different sensor data. The joint optimization of code layout and the order in which the different sensors should be sampled—in order to maximize code cache reuse—turns out to be a difficult combinatorial optimization problem. But our experiments show that optimizing the sampling order of the sensors has a much larger influence on cache reuse, compared to the effects that different code layouts have. Based on this, we also propose a heuristic that obtains near-optimal solutions in jointly optimizing both code layout as well the sensor sampling order. Our case study using a faint fall detection application—from the geriatric care domain—which is fed by a number of smart sensors to detect physiological and physical gait signals of a patient show very attractive power consumption in the underlying processor. Alternatively, our method can be used to improve the sampling frequency of the sensors, leading to higher reliability and better response time of the application.
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A preliminary version of this paper appeared in the Proc. International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS) 2008, and was nominated for a Best Paper Award.
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Ju, L., Liang, Y., Chakraborty, S. et al. Cache-aware optimization of BAN applications. Des Autom Embed Syst 13, 159–178 (2009). https://doi.org/10.1007/s10617-009-9045-3
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DOI: https://doi.org/10.1007/s10617-009-9045-3