Design and Analysis of a Heterojunction Vertical t-Shaped Tunnel Field Effect Transistor

Abstract

In this paper, a heterojunction vertical t-shaped tunnel field effect transistor (V-tTFET) is proposed, and the scaling issue associated with it is investigated using Sentaurus Technology computer-aided design simulation. This device is basically a gated P-I-N diode. It is made up of silicon material with dual gate control over the channel based on a band-to-band tunneling mechanism. Furthermore, a silicon-germanium (SiGe) layer is introduced to the channel which results in an aggressive improvement in the input characteristics of the device. The testified results of the device with respect to threshold voltage (V_T), subthreshold slope and the current ratio (I_on/I_off) emerges efficiently with the values of 0.253 V, 31.05 mV/decade and 10¹² for a 60-nm channel length with a 10-nm SiGe layer. A lower bandgap material in the source region and higher bandgap material in the drain region also improves the input characteristics of the device. It is also demonstrated that scaling the gate oxide thickness (t_ox) enhances the device characteristics. Moreover, ON-state current increases exponentially by taking the high value of the dielectric constant (k) for the oxide material. Furthermore, the (p++) source doping concentration of the V-tTFET lies between 10¹⁸ to 10²⁰ cm⁻³ which makes the tunneling easier at the source-channel junction to achieve high I_on/I_off. The vertical tunnel FET has a distribution of the source channel drain in the vertical direction, which enhances the scalability of the simulated device.